[1]侯春阳,李龙,张永维,等.DTECS系统高速数字电路的信号完整性仿真设计[J].机车电传动,2014,(04):48-52.[doi:10.13890/j.issn.1000-128x.2014.04.013]
 HOU Chun-yang,LI Long,ZHANG Yong-wei,et al.Design of Signal Integrality Simulation in High-speed Digital Circuit for DTECS[J].Electric Drive for Locomotives,2014,(04):48-52.[doi:10.13890/j.issn.1000-128x.2014.04.013]
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DTECS系统高速数字电路的信号完整性仿真设计()
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机车电传动[ISSN:1000-128X/CN:43-1125/U]

卷:
期数:
2014年04期
页码:
48-52
栏目:
研究开发
出版日期:
2014-07-10

文章信息/Info

Title:
Design of Signal Integrality Simulation in High-speed Digital Circuit for DTECS
文章编号:
1000-128X(2014)04-0048-05
作者:
侯春阳李龙张永维石力
南车电气技术与材料工程研究院
Author(s):
HOU Chun-yangLI LongZHANG Yong-weiSHI Li
(CSR Research of Electrical Technology & Material Engineering, Zhuzhou, Hunan 412001, China)
关键词:
信号完整性高速数字电路DDR端接匹配串扰列车分布式网络控制系统(DTECS)
Keywords:
signal integrity high-speed digital circuit DDR matched resistance crosstalk distribute train electric control system
分类号:
TP391.9;TP393
DOI:
10.13890/j.issn.1000-128x.2014.04.013
文献标志码:
A
摘要:
为提高列车分布式网络控制系统的硬件可靠性,对高速数字电路的信号完整性问题进行了仿真研究。首先介绍了信号完整性仿真的方法和工具,然后通过DDR仿真实例,在波形分析、端接匹配分析、串扰分析、同步开关噪声分析等方面,详细论述了信号完整性的仿真策略。试验测试结果表明,测试波形信号完整性良好,仿真结果和测试结果相吻合,验证了该仿真方法的可靠性和实用性。
Abstract:
In order to enhance hardware reliability of distribute train electric control system, the signal integrity problems of high-speed digital circuit was simulated and studied. Simulation methods and tools were introduced, and with an example of DDR circuit, signal integrity simulation analysis of wave, matched resistance, crosstalk, and switching noise were discussed in detail. The simulation results and the test results were consistent which verified the reliability of the methods.

参考文献/References:

[1] 向开福. 基于Cadence仿真工具的高速PCB系统设计[J]. 船舶电子对抗,2007,30(2).
[2] 赵海舜,王志平,季晓燕. 基于Cadence的DDR仿真设计[J]. 协议算法及仿真,2010,8(23):221.
[3] 张钦,韩翼中. 嵌入式存储系统的仿真与实现[J]. 计算机工程,2007,12(33).
[4] Stephen H. 高速数字系统设计[M]. 北京:机械工业出版社,2005:8-10.

备注/Memo

备注/Memo:
作者简介:侯春阳(1986-),女,工程师,主要从事列车网络控制系统硬件研发工作。
更新日期/Last Update: 2014-07-10